In sub-micron Complimentary Metal-Oxide Semiconductor (CMOS) manufacturing self-aligned contact (SAC) technology has been successfully used to achieve chip size reduction. In conventional SAC processes, gate film stacks are formed that include a hardmask or “capping layer” that extends over each gate electrode. An etch stop layer (e.g., silicon nitride) is deposited over the substrate and a pre-metal dielectric film is formed over the etch stop layer. An etch is then performed to form contact openings that extend through the pre metal dielectric film. This etch stops on the etch stop layer. The exposed portions of the etch stop layer are then removed, exposing the structure that is to be contacted. A metal layer is then deposited and planarized to complete the self-aligned contact. The etch stop layer and the capping layer align the contact with the structure to be contacted, preventing current leakage that could result from improper alignment.
Though the capping layer is effective for preventing shorting of the self-aligned contact to the gate electrode, it adds significant height to the gate film stack. Because of the close spacing between gate film stacks, this added height results in a structure that is difficult to fill with dielectric, producing voids that can cause bridging defects. In addition, the capping layer must be removed in order to contact gate electrodes, adding an etch step and an additional mask to the fabrication process.
Accordingly there is a need for a CMOS structure and a process for forming CMOS devices that gives good gap-fill characteristics between adjacent gate film stacks. Also, there is a need for a CMOS structure and a process for forming CMOS devices that do not have bridging defects. In addition, there is a need for a process for forming CMOS devices that reduces the number of masking and etching steps. The present invention meets the above needs.